There's a some useful info here :
https://www.youtube.com/watch?v=TGjUHChO1kM
The ADC uses its own clock so you're unlikely to be able to get cycle accurate timing.
Its going to take upto 1/12 of the 96 clock cycles per bit i.e <8 cycles per bit so the sampling has to occur within the first 8 clock cycles (even if the 'next' sample is concurrent with data output cycles).
Given the 1pf SAH cap has to charge , allowing 8 cycles (~170uS) seems reasonable
https://www.youtube.com/watch?v=TGjUHChO1kM
The ADC uses its own clock so you're unlikely to be able to get cycle accurate timing.
Its going to take upto 1/12 of the 96 clock cycles per bit i.e <8 cycles per bit so the sampling has to occur within the first 8 clock cycles (even if the 'next' sample is concurrent with data output cycles).
Given the 1pf SAH cap has to charge , allowing 8 cycles (~170uS) seems reasonable
Statistics: Posted by BillTodd — Tue Jan 30, 2024 9:30 am
